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White Electronic Designs
WV3HG2256M72AER-D6
ADVANCED*
4GB - 2x256Mx72 DDR2 SDRAM RDIMM, w/PLL
FEATURES
240-pin, dual in-line memory module (DIMM) Fast data transfer rates: PC2-6400*, PC2-5300*, PC2-4300 and PC2-3200 Support ECC error detection and correction VCC = VCCQ = 1.8V 0.1V VCCSPD = +1.7V to +3.6V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture DLL to align DQ and DQS transitions with CK Multiple internal device banks for concurrent operation Supports duplicate output strobe (RDQS/RDQS#) Programmable CAS# latency (CL): 3, 4, 5* and 6* Adjustable data-output drive strength On-die termination (ODT) Serial Presence Detect (SPD) with EEPROM Auto & self refresh: 64ms 8,192 cycle refresh Gold edge contacts RoHS compliant Dual Rank Package option * 240 Pin DIMM * PCB -30.00mm (1.181") TYP
NOTE: Consult factory for availability of: * Vendor source control options * Industrial temperature option * This product is under development, is not qualified or characterized and is subject to change without notice.
DESCRIPTION
The WV3HG2256M72AER is a 2x256Mx72 Double Data Rate DDR2 SDRAM high density module based on 1Gb DDR2 SDRAM components. This memory module consists of eighteen stacks of 256Mx4 bit with 8 banks DDR2 Synchronous DRAMs in FBGA packages, two - 14 bit registered buffers in BGA packages mounted on a 240-pin DIMM FR4 substrate.
OPERATING FREQUENCIES
PC2-3200 Clock Speed CL-tRCD-tRP
* Consult factory for availability
PC2-4300 266MHz 4-4-4
PC2-5300* 333MHz 5-5-5
PC2-6400* 400MHz 6-6-6
200MHz 3-3-3
April 2006 Rev. 1
1
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PIN CONFIGURATION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 April 2006 Rev. 1 Symbol VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS RESET# NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CB2 CB3 VSS VCCQ CKE0 VCC BA2 NC VCCQ A11 A7 VCC A5 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Symbol A4 VCCQ A2 VCC VSS VSS VCC NC VCC A10/AP BA0 VCCQ WE# CAS# VCCQ CS1# ODT1 VCCQ VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Symbol VSS DQ4 DQ5 VSS DM0/DQS9 NC/DQS9# VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1/DQS10 NC/DQS10# VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2/DQS11 NC/DQS11# VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3/DQS12 NC/DQS12# VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8DQS17 NC/DQS17# VSS CB6 CB7 VSS VCCQ CKE1 VCC NC NC VCCQ A12 A9 VCC A8 A6 Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Symbol VCCQ A3 A1 VCC CK0 CK0# VCC A0 VCC BA1 VCCQ RAS# CS0# VCCQ ODT0 A13 VCC VSS DQ36 DQ37 VSS DM4/DQS13 NC/DQS13# VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5/DQS14 NC/DQS14# VSS DQ46 DQ47 VSS DQ52 DQ53 VSS NC NC VSS DM6/DQS15 NC/DQS15# VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7/DQS16 NC/DQS16# VSS DQ62 DQ63 VSS VCCSPD SA0 SA1 2
WV3HG2256M72AER-D6
ADVANCED
PIN NAMES
Pin Name A0-A13 BA0,BA2 DQ0-DQ63 CB0-CB7 DQS0-DQS17 DQS0#-DQS17# DM0-DM8 ODT0, ODT1 CK0,CK0# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# RESET# SA0-SA2 SDA SCL VCC VCCQ VSS VREF VCCSPD NC Function Address Inputs SDRAM Bank Address Data Input/Output Check Bits Data strobes Data strobes complement Data Masks On-die termination control Clock Inputs, positive line Clock Enables Chip Selects Row Address Strobe Column Address Strobe Write Enable Register Reset Input SPD address SPD Data Input/Output SPD Clock Input Core Power I/O Power Ground Power Supply for Reference SPD Power supply No connect
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WV3HG2256M72AER-D6
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
VSS RCS1# RCS0# DQS0 DQS0#
DM CS# DQS DQS# DM CS# DQS DQS#
DM0/DQS9 NC/DQS9#
DM CS# DQS DQS# DM CS# DQS DQS#
DQ0 DQ1 DQ2 DQ3 DQS1 DQS1# DQ8 DQ9 DQ10 DQ11 DQS2 DQS2#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ4 DQ5 DQ6 DQ7 DM1/DQS10 NC/DQS10#
CS# DQS DQS#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
DM
CS# DQS DQS#
DM
CS# DQS DQS#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ12 DQ13 DQ14 DQ15 DM2/DQS11 NC/DQS11#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ16 DQ17 DQ18 DQ19 DQS3 DQS3#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ20 DQ21 DQ22 DQ23 DM3/DQS12 NC/DQS12#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ24 DQ25 DQ26 DQ27 DQS4 DQS4#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ28 DQ29 DQ30 DQ31 DM4/DQS13 NC/DQS13#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ32 DQ33 DQ34 DQ35 DQS5 DQS5#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ36 DQ37 DQ38 DQ39 DM5/DQS14 NC/DQS14#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ40 DQ41 DQ42 DQ43 DQS6 DQS6#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ44 DQ45 DQ46 DQ47 DM6/DQS15 NC/DQS15#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ48 DQ49 DQ50 DQ51 DQS#7 DQS7#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ52 DQ53 DQ54 DQ55 DM7/DQS16 NC/DQS16#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ56 DQ57 DQ58 DQ59 DQS8 DQS8#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DQ60 DQ61 DQ62 DQ63 DM8/DQS17 NC/DQS17#
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
CB0 CB1 CB2 CB3
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
CB4 CB5 CB6 CB7
I/O 0 I/O 1 I/O 2 I/O 3
I/O 0 I/O 1 I/O 2 I/O 3
VCCSPD
CS0# CS1# BA0-BA2 A0-A13 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 RESET#** PCK7** PCK7#**
Serial PD DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs
1:2
R E G I S T E R
RST#
RCS0# CS# : DDR2 SDRAMs RCS1# CS# : DDR2 SDRAMs RBA0-RBA2 BA0-BA2 : DDR2 SDRAMs RA0-RA13 A0-A13 : DDR2 SDRAMs RRAS# RAS# : DDR2 SDRAMs RCAS# CAS# : DDR2 SDRAMs RWE# WE# : DDR2 SDRAMs SCL RCKE0 CKE : DDR2 SDRAMs RCKE1 CKE : DDR2 SDRAMs RODT0 ODT : DDR2 SDRAMs RODT1 ODT : DDR2 SDRAMs
VCC/VCCQ VREF
Serial PD
VSS
SDA
WP A0
A1
A2
SA0 SA1 SA2
CK0 CK0# RESET#**
P L L
OE
PCK0-PCK6, PCK8, PCK9
CK : DDR2 SDRAMs CK# : DDR2 SDRAMs
PCK0#-PCK6#, PCK8#, PCK9# PCK7 CK : Register PCK7# CK# : Register
NOTE: All resistor values are 22 ohms unless otherwise specified. ** RESET#, PCK7 and PCK7# connect to both registers. Other signals connect to one of two registers.
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All Voltages Referenced to VSS Rating Parameter Supply Voltage I/O Input Reference Voltage I/O Termination Voltage SPD Supply Voltage Symbol VCC VREF VTT VCCSPD Min. 1.7 0.49*VCC VREF-0.04 1.7 Type 1.8 0.50*VCC VREF --
WV3HG2256M72AER-D6
ADVANCED
RECOMMENDED DC OPERATING CONDITIONS
Max. 1.9 0.51*VCC VREF+0.04 3.6
Units V V V V
Notes 3 1 2
Notes: 1. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed 2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 3. VCCQ of all IC's are tied to VCC.
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VIN, VOUT TSTG Parameter Voltage on VCC pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Command/Address, RAS#, CAS#, WE#, CS#, CKE CK, CK# DM DQ, DQS, DQS# Min -0.5 -0.5 -55 Max 2.3 2.3 100 Units V V C
IL
Input leakage current; Any input 0V-10
10
A
IOZ IVREF
Output leakage current; 0V-10 -72
10 72
A A
CAPACITANCE
TA = 25C, f = 100MHz, VCC = 1.8V Parameter Input Capacitance: (A0 ~ A13, BA0 ~ BA2, RAS#, CAS#, WE#) Input Capacitance: (CKE0, CKE1), (ODT0, ODT1) Input Capacitance: (CS0#, CS1#) Input Capacitance: (CK0, CK0#) Input Capacitance: (DM0 ~ DM8), (DQS0 ~ DQ17) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 (665) CIN5 (534, 403) COUT1 (665) COUT1 (534, 403) Min 10 10 10 10 9 9 9 9 Max 12 12 12 11 11 12 11 12 Units pF pF pF pF pF pF pF pF
Input/Output Capacitance: (DQ0 ~ DQ63), (CB0 ~ CB7)
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WV3HG2256M72AER-D6
ADVANCED
OPERATING TEMPERATURE CONDITION
Parameter Operating temperature (commercial) Symbol TOPER Rating 0 to +85C Units C Notes 1, 2
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2 2. At 0C to +85C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS Parameter Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.300 Max VCC + 0.300 VREF - 0.125 Units V V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS Parameter AC Input High (Logic 1) Voltage DDR2-400 & DDR-533 AC Input High ( Logic 1) Voltage DDR2-667* AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533 AC Input Low (Logic 0) Voltage DDR2-667* * Consult factory for availability Symbol VIH(AC) VIH(AC) VIL(AC) VIL(AC) Min VREF + 0.250 VREF + 0.200 Max VREF - 0.250 VREF - 0.200 Units V V V V
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VCC = +1.8V 0.1V Symbol Proposed Conditions ICC0*
WV3HG2256M72AER-D6
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
806
TBD
665 2,336
534 2,246
403 2,156
Units mA
Operating one bank active-precharge current; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1
ICC1*
TBD
2,516
2,426
2,336
mA
ICC2P**
TBD
932
932
932
mA
ICC2Q**
TBD
1,940
1,760
1,760
mA
ICC2N**
TBD
2,120 1,580 932
1,940 1,400 932
1,940 1,400 932
mA mA mA
TBD TBD
ICC3P**
ICC3N**
Active standby current; All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING
TBD
2,300
2,120
2,120
mA
ICC4W*
TBD
3,056
2,876
2,516
mA
ICC4R*
TBD
3,056
2,876
2,516
mA
ICC5B**
TBD
8,420
8,240
8,060
mA
ICC6**
Normal
TBD
360
360
360
mA
ICC7*
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as ICC4R; Refer to the following page for detailed timing conditions
TBD
6,116
5,756
5,396
mA
Note: ICC specs are based on SAMSUNG components. Other DRAM manufacturers parameters may be different. * Value calculated as one module rank in this operation condition, and all other module ranks in ICC2P (CKE LOW) mode.
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AC TIMING PARAMETERS
VCC = +1.8V 0.1V AC Characteristics Parameter CL = 6 Clock cycle time CL = 5 CL = 4 CL = 3 Clock CK high-level width CK low-level width Half clock period Clock jitter DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS Data DQ and DM input hold time relative to DQS DQ...DQS hold, DQS to first DQ to go nonvalid, per access relative to DQS Data hold skew factor DQ-DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# Data Strobe DQS falling edge to CK rising- setup time DQS falling edge from CK rising - hold time DQS-DQ skew, DQS to last DQ valid, per group, per access DQS read preamble Symbol tCK (6) tCK (5) tCK (4) tCK (3) tCH tCL tHP tJIT tAC tHZ tLZ tDS tDH tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS tDSH tDQSQ tRPRE Min
TBD TBD TBD TBD TBD TBD
WV3HG2256M72AER-D6
ADVANCED
806 Max
TBD TBD TBD TBD TBD TBD
665 Min Max Min
534 Max Min
403 Max Unit ps
3,000 3,750 5,000 0.45 0.45 MIN (tCH, tCL)
-125
8,000 8,000 8,000 0.55 0.55 3,750 5,000 0.45 0.45 MIN (tCH, tCL) 125 +450 tAC (MAX)
-125
ps 8,000 8,000 0.55 0.55 5,000 5,000 0.45 0.45 MIN (tCH, tCL) 125 +500 tAC (MAX) tAC
(MIN) -125
8,000 8,000 0.55 0.55
ps ps tCK tCK ps
TBD
TBD
TBD TBD TBD TBD TBD
125 +600 tAC (MAX)
ps ps ps ps tCK ps ps
-450
-500
-600
TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD
tAC
(MIN)
tAC
(MAX)
tAC
(MAX)
tAC
(MIN)
tAC
(MAX)
100 175 0.35 340 tHPtQHS tQHtDQSQ 0.35 0.35 -400 0.2 0.2 240 0.9 1.1 +400
100 225 0.35 400 tHPtQHS tQHtDQSQ 0.35 0.35 -450 0.2 0.2 300 0.9 1.1 +450
150 275 0.35 450 tHPtQHS tQHtDQSQ 0.35 0.35 -500 0.2 0.2 350 0.9 1.1 +500
TBD TBD TBD TBD
TBD TBD TBD TBD
tCK tCK ps tCK tCK ps tCK
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Note: * AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Continued on next page
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VCC = +1.8V 0.1V AC Characteristics Parameter DQS read preamble Data Strobe DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition Address and control input pulse width for each input Address and control input setup time Address and control input hold time CAS# to CAS# command delay Active to Active (same bank) command Active bank a to Active b bank command Command and Address Active to Read or Write delay Four Bank Activate period Active to precharge command Internal Read to precharge command delay Write recovery time Auto precharge write recovery and precharge time Interval Write to Read command delay Precharge command period Precharge All command period Load Mode command cycle time CKE low to CK,CK# uncertainty Symbol tRPST tWPRES tWPRE tWPST tDQSS tIPW tISa tIHa tCCD tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD tDELAY Min
TBD TBD TBD TBD TBD
WV3HG2256M72AER-D6
ADVANCED
AC TIMING PARAMETERS (Continued)
806 Max
TBD TBD TBD TBD TBD
665 Min 0.4 0 0.35 0.4
WL-0.25
534 Max 0.6 Min 0.4 0 0.35 0.6 0.4
WL-0.25
403 Max 0.6 Min 0.4 0 0.35 0.6 0.4
WL-0.25
Max 0.6
Unit tCK ps tCK
0.6
WL+0.25
tCK tCK tCK ps ps tCK ns ns ns
WL+0.25
WL+0.25
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
0.6 200 275 2 54 7.5 15 37.5 39 7.5 15 tWR+tRP 7.5 15 tRP+tCK 2 tIS+tCK
+tIH
0.6 250 375 2 55 7.5 15 37.5 70,000 37.5 40 7.5 15 tWR+tRP 7.5 15 tRP+tCK 2 tIS+tCK
+tIH
0.6 350 475 2 55 7.5 15 37.5 70,000 37.5 40 7.5 15 tWR+tRP 10 15 tRP+tCK 2 tIS+tCK
+tIH
37.5 70,000
ns ns ns ns ns ns ns ns tCK ns
TBD
TBD
Note: * AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Continued on next page
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VCC = +1.8V 0.1V AC Characteristics Parameter Refresh to Active or Refresh to Refresh command interval Average periodic refresh interval Exit self refresh to non-read command Exit self refresh to read command Exit self refresh timing reference ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off ODT Symbol tRFC tREFI tXSNR tXSRD tISXR tAOND tAON tAOFD tAOF Min
TBD TBD TBD TBD TBD TBD
WV3HG2256M72AER-D6
ADVANCED
AC TIMING PARAMETERS (Continued)
806 Max
TBD TBD TBD TBD TBD TBD
665 Min 127.5 Max 70,000 7.8 tRFC
(MIN)+10
534 Min 127.5 Max 70,000 7.8 tRFC
(MIN)+10
403 Min 127.5 Max 70,000 7.8 tRFC
(MIN)+10
Unit ns s ns tCK ps
200 tIS 2 tAC(MIN) 2.5 tAC(MIN)
tAC(MIN)
200 tIS 2 tAC(MAX) +1,000 2.5 tAC(MAX) +600
2x tCK + tAC (MAX) + 1,000 2.5x tCK + tAC (MAX) + 1,000
200 tIS 2 tAC(MAX) +1,000 2.5 tAC(MAX) +600
2x tCK + tAC (MAX) + 1,000 2.5x tCK + tAC (MAX) + 1,000
2 tAC(MIN) 2.5 tAC(MIN)
tAC(MIN) +2,000 tAC(MIN) +2,000
2 tAC(MIN) 2.5 tAC(MIN)
tAC(MIN) +2,000 tAC(MIN) +2,000
2 tAC(MAX) +1,000 2.5 tAC(MAX) +600
2x tCK + tAC (MAX) + 1,000 2.5x tCK + tAC (MAX) + 1,000
tCK ps tCK ps
TBD
TBD
TBD
TBD
TBD
TBD
ODT turn-on (power-down mode)
tAONPD
TBD
TBD
+2,000 tAC(MIN)
ps
ODT turn-off (power-down mode) ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Power-Down Exit active power-down to READ command, MR[bit12=1] Exit precharge power-down to any nonREAD command. CKE minimum high/low time
tAOFPD tANPD tAXPD tXARD tXARDS tXP tCKE
TBD
TBD
+2,000
tCK tCK tCK tCK tCK tCK tCK
TBD TBD TBD
TBD TBD TBD
3 8 2 7-AL 2 3
3 8 2 6-AL 2 3
3 8 2 6-AL 2 3
TBD
TBD
TBD TBD
TBD TBD
Note: * AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
April 2006 Rev. 1
9
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WV3HG2256M72AER-D6
ADVANCED
ORDERING INFORMATION FOR D6
Part Number W3HG2256M72ACER806D6xxG** W3HG2256M72ACER665D6xxG** W3HG2256M72ACER534D6xxG W3HG2256M72ACER403D6xxG Speed/Data Rate 400MHz/800Mb/s 333MHz/667Mb/s 266MHz/533Mb/s 200MHz/400Mb/s CAS Latency 6 5 4 3 tRCD 6 5 4 3 tRP 6 5 4 3 Height* 30.00mm (1.181") TYP 30.00mm (1.181") TYP 30.00mm (1.181") TYP 30.00mm (1.181") TYP
** Contact factory for availability Notes: * RoHS compliant product. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR D6
FRONT VIEW
133.50 (5.256) 133.20 (5.244)
3.00 (0.118)
(4X)
4.00 (0.158)
(4X) 30.50 (1.201) 29.851 (1.175) 17.80 (0.700) TYP.
0.270 (6.73) MAX
5.175 (0.204)
(2X)
PIN 1 1.0 (0.039) TYP. 0.80 (0.032) TYP. 1.50 (0.059) 10.00 (0.394) TYP. PIN 120
4.843 (123.0) TYP.
BACK VIEW
1.37 (0.054) 1.17 (0.046)
PIN 240
63.0 (2.480) TYP.
5.0 (0.197) TYP. 55.0 (2.165) TYP.
PIN 121
Detail B
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
April 2006 Rev. 1
10
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WV3HG2256M72AER-D6
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 2 256M 72 A E R xxx D6 x x G
WEDC MEMORY (SDRAM) DDR 2 GOLD DUAL RANK DEPTH BUS WIDTH COMPONENT WIDTH x4 1.8V REGISTERED SPEED (Mb/s) PACKAGE 240 PIN DIMM INDUSTRIAL TEMP OPTION (For commercial leave "blank" for industrial add "I") COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT
April 2006 Rev. 1
11
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
4GB - 2x256Mx72 DDR2 SDRAM REGISTERED, w/PLL DRAM DIE OPTIONS: * SAMSUNG: A-Die, will move to B-Die Q1'07 * MICRON: U28A: A-Die, will move to U38Z: D-Die Q4'06
WV3HG2256M72AER-D6
ADVANCED
Revision History Rev #
Rev 0 Rev 1
History
Evaluation and review 1.0 Update VCC specifications 1.1 Moved from concept to advanced 1.2 Added DRAM die verification
Release Date
March 2006 April 2006
Status
Concept Advanced
April 2006 Rev. 1
12
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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